Release Notes Last updated 07.02.2012 by DB ************** * PVProHD-AV * ************** From: PVPro_HD_CUK_AV_1-6-3a_7718.brec To: PVPro_HD_CUK_AV_1-6-3b_7993.brec Release Date: 07.02.2012 Changes implemented are: 1. HDMI mode recognition corrected. -------------- From: PVPro_HD_CUK_AV_1-6-0_6753.brec To: PVPro_HD_CUK_AV_1-6-3a_7718.brec Release Date: 10.10.2011 Changes implemented are: 1. Improved genlock such that also main board rev. 1.2 is usable. Main board 1.1b was working before, but was marginal. 2. Improved HDCP authorisation failed message time to display. 3. Web Browser support implemented. 4. File Upload of Test Patterns implemented. 5. HDCP negotiation improved. 6. 24Hz output frame rate with 24Hz Genlock source supported. This works only in conjunction with latest Genlock boards having genlock_fpga2_iss5.pof and genlockhd18.hex programmed to the FPGA and PIC. ************** * PVProHD-DC * ************** From: PVPro_HD_DC_1-6-3A_7688.brec To: PVPro_HD_DC_1-6-3A_7718.brec Release Date: 10.10.2011 Changes implemented are: 1. File Upload improved, now supporting 4MByte files. 2. Memory allocation changed. USB device not running properly (only for internal purpose). ------------- From: PVPro_HD_DC_1-6-3_7632.brec To: PVPro_HD_DC_1-6-3A_7688.brec Release Date: 01.09.2011 Changes implemented are: 1. Pan and Tilt now works for shrink (horizontal/vertical zoom <100%). ------------- From: PVPro_HD_DC_1-6-2A_7385.brec To: PVPro_HD_DC_1-6-3_7632.brec Release Date: 09.08.2011 Changes implemented are: 1. Web Browser support implemented. 2. File Upload implemented, Test Patterns and Alpha Map. 3. HDCP negotiation improved. 4. 24Hz output frame rate with 24Hz Genlock source (incl. 3D 24Hz modes) supported. This works only in conjunction with latest Genlock boards having genlock_fpga2_iss5.pof and genlockhd18.hex programmed to the FPGA and PIC. 5. General improvement of Genlock for 2D <-> 3D timing switching in real life player operation. -------------- From: PVPro_HD_DC_1-6-1_7219.brec To: PVPro_HD_DC_1-6-2A_7385.brec Release Date: 26.04.2011 Changes implemented are: 1. 3D input format recognition and Left/Right Eye extraction implemented. Under Output Setting/3D Extract left/right output can be set-up. 2. Improved genlock such that also main board rev. 1.2 is usable. Main board 1.1b was working before, but was marginal. 3. Improved HDCP authorisation failed message time to display. -------------- From: PVPro_HD_DC_1-6-0A_7070.brec To: PVPro_HD_DC_1-6-1_7219.brec Release Date: 01.03.2011 Changes implemented are: 1. Warp Uploads from PC Warp Generator not working for certain hardware (main board version 1.1b with M-die flash) with bootloader version 1.1 Type-K not working fixed. 2. Warp fields are analyzed at runtime regarding engine processing time. Skipped frames due to insufficient bandwidth are recognized once a warp is set-up. The warp field is not applied and a message is displayed in the LCD menu screen "Slow WARP - frame skipped". This mechanism is on top of the "TOO EXTREME" estimate of the embedded WARP library. *************** * PVProHD-LED * *************** From: PVPro_HD_CUK_LED_1-6-1_7221.brec To: PVPro_HD_CUK_LED_1-6-2A_7370.brec Release Date: 26.04.2011 Changes implemented are: 1. 3D input format recognition and Left/Right Eye extraction implemented. Under Output Setting/3D Extract left/right output can be set-up. 2. Improved genlock such that also main board rev. 1.2 is usable. Main board 1.1b was working before, but was marginal. 3. Improved HDCP authorisation failed message time to display. --------------- From: PVPro_HD_CUK_LED_1-6-0A_7064.brec To: PVPro_HD_CUK_LED_1-6-1_7221.brec Release Date: 01.03.2011 Changes implemented are: 1. HDSDI modes with 23.98, 29.97 or 59.94Hz are displayed with wrong color has been fixed. ************** * PVProHD-IW * ************** From: PVPro_HD_CUK_IW_1-6-3_7632.brec To: PVPro_HD_CUK_IW_1-6-3A_7716.brec Release Date: 10.10.2011 Changes implemented are: 1. File Upload improved, now supporting 4MByte files. 2. Memory allocation changed (USB device in live operation for internal use). -------------- From: PVPro_HD_CUK_IW_1-6-2A_7385.brec To: PVPro_HD_CUK_IW_1-6-3_7632.brec Release Date: 09.08.2011 Changes implemented are: 1. Web Browser support implemented. 2. File Upload implemented, Test Patterns and Alpha Map. 3. HDCP negotiation improved. 4. 24Hz output frame rate with 24Hz Genlock source (incl. 3D 24Hz modes) supported. This works only in conjunction with latest Genlock boards having genlock_fpga2_iss5.pof and genlockhd18.hex programmed to the FPGA and PIC. 5. General improvement of Genlock for 2D <-> 3D timing switching in real life player operation. -------------- From: PVPro_HD_CUK_IW_1-6-1_7219.brec To: PVPro_HD_CUK_IW_1-6-2A_7385.brec Release Date: 26.04.2011 Changes implemented are: 1. 3D input format recognition and Left/Right Eye extraction implemented. Under Output Setting/3D Extract left/right output can be set-up. 2. Improved genlock such that also main board rev. 1.2 is usable. Main board 1.1b was working before, but was marginal. 3. Improved HDCP authorisation failed message time to display. -------------- From: PVPro_HD_CUK_IW_1-6-0C_7170.brec To: PVPro_HD_CUK_IW_1-6-1_7219.brec Release Date: 01.03.2011 Changes implemented are: 1. Warp fields are analyzed at runtime regarding engine processing time. Skipped frames due to insufficient bandwidth are recognized once a warp is set-up. The warp field is not applied and a message is displayed in the LCD menu screen "Slow WARP - frame skipped". This mechanism is on top of the "TOO EXTREME" estimate of the embedded WARP library.